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TC9WMA2FK 2007-10-19 1 toshiba cmos digital integrated circuits silicon monolithic TC9WMA2FK 2,048-bit (256 8 bit) serial e 2 prom the TC9WMA2FK is electrically erasable/programmable nonvolatile memory (e 2 prom). features ? serial data input/output ? programmable in units of one word and collectively erasable in one operation ? automatically set programming time (built-in timer) ? programming time: 10 ms (max) (v cc = 3.0 to 5.5 v) 12 ms (max) (v cc = 2.3 to 2.7 v) ? overwrite enabled or disabled by software ? single power supply and low power consumption ? operating voltage range for reading: v cc = 1.8 to 5.5 v ? operating voltage range for writing: v cc = 2.3 to 5.5 v ? wide operating temperature range ( ? 40 to 85c) product marking pin assignment (top view) weight: 0.01 g (typ.) cs 8 di do 76 5 1234 gnd nc rst v cc clk type name us8 9wm a2 no.1 pin indicator
TC9WMA2FK 2007-10-19 2 block diagram pin function pin name input/output function cs input chip select a low on cs selects the chip. always return cs high temporarily before executing instructions. clk input clock input the data on di is latched by a rising edge of clk . data is output to do by a falling edge of clk . clk is effective when cs is low. di input serial data input this pin is used to enter addresses, commands, and data into the chip. do output serial data output this pin outputs data from the chip. rst input reset input a low on this input resets the chip. nc ? no connection (not connected internally) v cc 1.8 v~5.5 v (for reading) 2.3~5.5 v (for writing) gnd power supply 0 v (gnd) control circuit address decoder power supply (booster circuit) memory cell data register timing generator address register chip select input/output circuit clock input data input di data output do v cc power supply reset input gnd ground command register rst clk cs
TC9WMA2FK 2007-10-19 3 functional description 1. types of instructions command operation address c0 c1 c2 c3 data read a0~a7 1 0 0 0 0 0 0 0 program a0~a7 0 1 1 0 0 0 0 0 d0~d7 all erase ******** 0011 0000 busy monitor ******** 1011 0000 overwrite enable ******** 1001 0000 overwrite disable ******** 1101 0000 read auto-incremented a0~a7 1 0 0 0 1 0 0 0 *: don?t care 2. operation method be sure to drive cs and clk high temporarily before entering an instruction. after cs is asserted low, clk ? read entering the read instruction causes memory data at the specified address to be read out and serially output from the do pin. ? program entering the program instruction ca uses overwrite operation to auto matically start within the chip, overwriting memory data at the spec ified address with the input data. after the instruction is entered, cs can be driven high even while overwrite operation is still in progress internally. ? all erase entering the erase all instruction causes erase op eration to automatically start within the chip, erasing memory data at all addresses. after the instruction is entered, cs can be driven high even while er ase operation is still in progress internally. this command clears the memory data to 0. ? busy monitor entering the monitor busy instruction causes a ready/busy status signal to be output from the do pin. this output signal is low while the chip is being programmed or collectively erased, and is high after programming or collective erase operation is completed. the ready/busy status signal is output continuously until cs is driven high. ? overwrite enable/disable entering the enable overwr ite instruction places the chip in overwrite enabled mode, where the program and erase all instructions can be entered. entering the disable overwrite instruction places the chip in overwrite disabled mode, where the program and erase all instructions cannot be entered. once the chip is placed in overwr ite disabled mode, it remains disa bled against overwriting until the enable overwrite instru ction is entered. ? read auto-incremented after the data at the specified address is output, the subsequent clk
TC9WMA2FK 2007-10-19 4 3. precautions on powering up or down the chip (1) a wait time of 1 ms is required before the chip can start operation after it is powered up. (2) ensure that rst is low when powering up or down the chip. (3) resetting the chip places it in overwrite disabled mode. 4. timing chart (1) read (2) program cs clk 1 2 7 8 9 10 11 12 13 14 15 16 17 24 23 a0 a1 0 a7 1 0 10 0 00 di do command address hi-z a6 d6 d7 d0 cs clk 1 2 7 8 9 10 11 12 13 14 15 16 17 24 23 a0 a1 1 a7 0 0 00 0 00 di do hi-z command address hi-z a6 d0 data d6 d7
TC9WMA2FK 2007-10-19 5 (3) all erase (4) busy monitor (5) overwrite enable/disable cs clk 1 2 7 8 9 10111213141516 1 0 0000 enable do command hi-z 0 1 1 1 0000 disable command 0 1 di cs clk 1 2 7 8 9 10 11 12 13 14 15 16 1 00000 di do command hi-z 1 0 cs clk 1 2 7 8 9 10 11 12 13 14 15 16 1 0 0000 di do command hi-z 1 1 hi-z
TC9WMA2FK 2007-10-19 6 (6) read auto-incremented cs clk 1 2 7 8 9 10 11 12 13 14 15 16 17 24 23 a0 0 01 0 0 di do hi-z command address hi-z data a0 ??? a7 address 25 32 31 33 39 40 a1 1 0 0 d0 d6 d7 d0 d6 d7 d0 d6 d7 data a0 ?? a7 + 1 address data a0 ?? a7 + 2 address a6 a7
TC9WMA2FK 2007-10-19 7 absolute maximum ratings (note) (gnd = 0 v) characteristics symbol rating unit power supply voltage v cc ? 0.3~7.0 v input voltage v in ? 0.3~v cc + 0.3 v output voltage v out ? 0.3~v cc + 0.3 v power dissipation p d 200 (25c) mw soldering temperature (in time) t sld 260 (10 s) c storage temperature t stg ? 55~125 c operating temperature t opr ? 40~85 c note: exceeding any of the absolute maximum ratings, even br iefly, lead to deterioration in ic performance or even destruction. using continuously under heavy loads (e.g. the app lication of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operat ing temperature/current/voltage, etc. ) are within the absolute maximum ratings and the operating ranges. please design the appropriate reliability upon reviewing the toshiba semiconductor reliability handbook (?handling precautions?/?derating concept and methods?) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). operating ranges (note 1) (gnd = 0 v, t opr = ? 40 to 85c) characteristics symbol test condition min max unit supply voltage (for reading) v cc 1.8 5.5 v supply voltage (for writing) v cc 2.3 5.5 v operating ranges (note 1) (v cc = 1.8 to 2.7 v, gnd = 0 v, t opr = ? 40 to 85c) 1.8 v < = v cc < 2.3 v 2.3 v < = v cc < 2.7 v characteristics symbol min max min max unit low level input voltage v il 0 0.15 v cc 0 0.35 v v ih1 (note 1) 0.7 v cc v cc 1.6 v cc high level input voltage v ih2 (note 2) 0.8 v cc v cc 1.8 v cc v operating frequency f clk 0 0.25 0 0.5 mhz operating ranges (note 1) (v cc = 2.7 to 5.5 v, gnd = 0 v, t opr = ? 40 to 85c) 2.7 v < = v cc < = 3.6 v 4.5 v < = v cc < = 5.5 v characteristics symbol min max min max unit low level input voltage v il 0 0.45 0 0.7 v v ih1 (note 2) 1.6 v cc 2.0 v cc high level input voltage v ih2 (note 3) 2.2 v cc 3.0 v cc v operating frequency f clk 0 1 0 1 mhz note 1: the operating ranges must be maintai ned to ensure the normal op eration of the device. unused inputs must be tied to either vcc or gnd. note 2: cs , di, rst note 3: clk
TC9WMA2FK 2007-10-19 8 electrical characteristics d.c. characteristics (v cc = 1.8 to 2.7 v, gnd = 0 v, t opr = ? 40 to 85c) 1.8 v < = v cc < 2.3 v 2.3 v < = v cc < 2.7 v characteristics symbol test condition min max min max unit input current i li ? 1 ? 1 a output leakage current i lo ? 1 ? 1 a i oh = ? 1 ma ? ? ? ? i oh = ? 500 a ? ? v cc ? 0.4 ? high level output voltage v oh i oh = ? 100 a v cc ? 0.2 ? ? ? v i ol = 2 ma ? ? ? ? i ol = 500 a ? ? 0.4 ? low level output voltage v ol i ol = 100 a 0.2 ? ? ? v quiescent supply current i cc1 (note 1) ? 5 ? 5 a supply current during read i cc2 (note 2) ? 0.5 ? 1.0 ma supply current during all erase/program i cc3 (note 3) ? ? ? 1.0 ma d.c. characteristics (v cc = 2.7 to 5.5 v, gnd = 0 v, t opr = ? 40 to 85c) 2.7 v < = v cc < 3.6 v 4.5 v < = v cc < = 5.5 v characteristics symbol test condition min max min max unit input current i li ? 1 ? 1 a output leakage current i lo ? 1 ? 1 a i oh = ? 1 ma v cc ? 0.4 ? v cc ? 0.4 ? i oh = ? 500 a ? ? ? ? high level output voltage v oh i oh = ? 100 a ? ? ? ? v i ol = 2 ma 0.4 ? 0.4 ? i ol = 500 a ? ? ? ? low level output voltage v ol i ol = 100 a ? ? ? ? v quiescent supply current i cc1 (note 1) ? 5 ? 5 a supply current during read i cc2 (note 2) ? 1.5 ? 2.5 ma supply current during all erase/program i cc3 (note 3) ? 1.0 ? 2.0 ma note 1: cs = 1 (except when busy, however) note 2: current that flows for a period between a fall of the 14th clk pulse and a rise of the 16th clk pulse when executing the read instruction. note 3: current that flows while executi ng the erase all or pr ogram instruction.
TC9WMA2FK 2007-10-19 9 a.c. characteristics (v cc = 1.8 to 2.7 v, gnd = 0 v, t opr = ? 40 to 85c) 1.8 v < = v cc < 2.3 v 2.3 v < = v cc < 2.7 v characteristics symbol test condition min max min max unit maximum clock frequency f max 0 0.25 0 0.5 mhz twclk (l) minimum clock pulse width twclk (h) 1.0 ? 1.0 ? s minimum reset pulse width t wrst 1 ? 1 ? s minimum chip select pulse width t wcs 1 ? 1 ? s reset setup time t rss rst setup time when cs is switched over 1 ? 1 ? s clock setup time t cks clk setup time when cs is switched over 500 ? 500 ? ns cs setup time t css cs setup time when clk is switched over 500 ? 500 ? ns t plh t phl t pzh t pzl time from clk switchover until valid data is output ? 2.0 ? 1.0 propagation delay time (note) t plz t phz time from cs switchover until output data goes hi-z ? 2.0 ? 1.0 s input data setup time t s input data setup time when clk is switched over 500 ? 500 ? ns input data hold time t h input data hold time when clk is switched over 500 ? 500 ? ns note: c l = 100 pf, r l = 1 k
TC9WMA2FK 2007-10-19 10 a.c. characteristics (v cc = 2.7 to 5.5 v, gnd = 0 v, t opr = ? 40 to 85c) 2.7 v < = v cc < = 3.6 v 4.5 v < = v cc < = 5.5 v characteristics symbol test condition min max min max unit maximum clock frequency f max 0 1 0 1 mhz twclk (l) minimum clock pulse width twclk (h) 0.4 ? 0.4 ? s minimum reset pulse width t wrst 1 ? 1 ? s minimum chip select pulse width t wcs 1 ? 1 ? s reset setup time t rss rst setup time when cs is switched over 1 ? 1 ? s clock setup time t cks clk setup time when cs is switched over 250 ? 250 ? ns cs setup time t css cs setup time when clk is switched over 250 ? 250 ? ns t plh t phl t pzh t pzl time from clk switchover until valid data is output ? 0.25 ? 0.25 propagation delay time (note) t plz t phz time from cs switchover until output data goes hi-z ? 0.5 ? 0.5 s input data setup time t s input data setup time when clk is switched over 250 ? 250 ? ns input data hold time t h input data hold time when clk is switched over 250 ? 250 ? ns note: c l = 100 pf, r l = 1 k
TC9WMA2FK 2007-10-19 11 e 2 prom characteristics (gnd = 0 v, 2.3 v < = v cc < = 2.7 v, t opr = ? 40 to 85c) characteristics symbol test condition min typ. max unit all erase time t e ? 12 ms program time t p ? 12 ms endurance n ew 1 10 5 ? ? times data retention time t ret 10 ? ? year e 2 prom characteristics (gnd = 0 v, 3.0 v < = v cc < = 5.5 v, t opr = ? 40 to 85c) characteristics symbol test condition min typ. max unit all erase time t e ? 10 ms program time t p ? 10 ms endurance n ew 1 10 5 ? ? times data retention time t ret 10 ? ? year capacitance characteristics (ta = 25c) characteristics symbol test condition v cc (v) typ. unit input capacitance c in 3.3 4 pf output capacitance c o 3.3 3 pf equivalent internal capacitance c pd f in = 1 mhz (note) 3.3 8.5 pf note: c pd denotes the ic?s internal equivalent capacitance calc ulated from the amount of cu rrent it consumes while operating. the average current consumption during non-loaded operation is obtained from the equations below. i cc (read) = f clk ?c pd ?v cc + i cc1 + i cc2 ?3/24 i cc (prog) = f clk ?c pd ?v cc + i cc1 + i cc3
TC9WMA2FK 2007-10-19 12 a.c. characteristics timing chart hiz t cks v cc cs v cc /2 t css t cks t css v cc /2 t s t h v cc /2 v cc /2 t plh t phl v cc /2 t plh t phl v cc /2 t plz t phz v cc /2 v cc /2 t pzh t pzl v cc /2 v cc /2 hiz t wclk (l) t wclk (h) v cc /2 v cc /2 gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd clk clk di clk do cs clk do clk do clk v cc /2 t wrst v cc /2 v cc gnd v cc gnd t rss v cc /2 t wcs v cc /2 v cc /2 rst cs rst cs v cc /2 v cc gnd t pzh t pzl v cc /2 t plh t phl v cc /2 v cc gnd clk do
TC9WMA2FK 2007-10-19 13 input/output circuits of pins pin name type input/output circuit remarks cs di rst input clk input hysteresis input do output initial ?hiz? output control signal v cc
TC9WMA2FK 2007-10-19 14 package dimensions weight: 0.01 g (typ.)
TC9WMA2FK 2007-10-19 15 restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (colle ctively ?toshiba?), reserve the right to make changes to the in formation in this document, and related hardware, software and systems (collectively ?product?) without notice. ? this document and any information herein may not be reproduced without prior written permission from toshiba. even with toshiba?s written permission, repro duction is permissible only if reproduction is without alteration/omission. ? though toshiba works continually to improve product?s quality and reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunc tion or failure of product could cause loss of human life, b odily injury or damage to property, including data loss or corrupti on. before creating and producing designs and using, customers mus t also refer to and comply with (a) the late st versions of all relevant toshiba info rmation, including without limitation, this d ocument, the specifications, the data sheets and application notes for pr oduct and the precautions and conditions set forth in the ?tosh iba semiconductor reliability handbook? and (b) the instructions for the application that product will be used with or for. custome rs are solely responsible for all aspects of th eir own product design or applications, incl uding but not limited to (a) determining th e appropriateness of the use of this product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample app lication circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. toshiba assumes no liability for customers? product design or applications. ? product is intended for use in general electronics application s (e.g., computers, personal equipment, office equipment, measur ing equipment, industrial robots and home el ectronics appliances) or for specific applicat ions as expressly stated in this document . product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality a nd/or reliability and/or a malfunction or failure of which may caus e loss of human life, bodily injury, serious property damage or se rious public impact (?unintended use?). unintended use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for au tomobiles, trains, ships and other transportation, traffic s ignaling equipment, equipment used to control comb ustions or explosions, safety devices, el evators and escalators, devices related to el ectric power, and equipment used in finance-rela ted fields. do not use product for unint ended use unless specifically permitted in thi s document. ? do not disassemble, analyze, reverse-engineer, alter, modify , translate or copy product, whether in whole or in part. ? product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. ? the information contained herein is presented only as guidance for product use. no responsibility is assumed by toshiba for an y infringement of patents or any other intellectual property rights of third parties that may result from the use of product. no license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise. ? absent a written signed agreement, except as provid ed in the relevant terms and conditions of sale for product, and to the maximum extent allowable by law, toshiba (1) assumes no liability whatsoever, including without limitation, indirect, co nsequential, special, or incidental damages or loss, including without limitation, loss of profit s, loss of opportunities, business interruption and loss of data, and (2) disclaims any and all express or implied warranties and conditions related to sale, use of product, or information, including warranties or conditions of merchantability, fitness for a particular purpose, accuracy of information, or noninfringement. ? do not use or otherwise make available product or related so ftware or technology for any military purposes, including without limitation, for the design, development, use, stockpiling or manuf acturing of nuclear, chemical, or biological weapons or missi le technology products (mass destruction weapons). product and related software and technology may be controlled under the japanese foreign exchange and foreign trade law and the u.s. ex port administration regulations. export and re-export of product or related software or technology are strictly prohibited ex cept in compliance with all app licable export laws and regulations. ? please contact your toshiba sales representative for details as to environmental matters such as the rohs compatibility of pro duct. please use product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled subs tances, including without limitation, the eu rohs directive. toshiba assu mes no liability for damages or losses occurring as a result o f noncompliance with applicable laws and regulations.

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